A non-volatile memory cell retains information stored in the memory cell even when the power is turned off. To create a non-volatile memory cell, typically a standard CMOS-based logic process is used as a starting foundation. Next, additional process steps are incorporated into the logic process flow to create the non-volatile memory cell. Examples of such additional process steps include second polysilicon deposition, junction dopant optimization, etc. Integrating “non-volatile memory”-specific process steps into the standard CMOS-based logic process creates complications. Consequently, embedded non-volatile memory technologies generally lag behind advanced logic fabrication processes by several generations. For a system-on-chip (SoC) approach, which requires embedding a non-volatile memory, a design team may have no choice but to accept a logic flow process usually two to three generations behind the current advanced standard logic process as well as the addition to that process of several additional lithographic masks. This prior approach not only typically increases the wafer cost, but it also falls short of the peak performance that the most advanced standard logic process can deliver.
Also, due to the cycling-induced degradation of the SiO2, the previous technique of subjecting all of the non-volatile memory cell components to the higher program and erase voltages typically hastens the degradation of the SiO2, thus degrading the performance and reliability of the non-volatile memory cell.
Structures and fabrication methods have therefore been explored to solve the above-discussed problems. U.S. Patent Publication No. 2007/0120172 provides a non-volatile memory cell 100, which is shown in FIG. 1. Memory cell 100 includes transistor 102, erase-tunneling capacitor 104, coupling capacitor 106, and program-tunneling capacitor 108. The erase-tunneling capacitor 104, coupling capacitor 106, and program-tunneling 108 share a common floating gate FG. Coupling capacitor 106 has a significantly greater capacitance than erase-tunneling capacitor 104 and program-tunneling 108 in order to facilitate efficient program and erase operations. In a program operation, program gate PG is applied with a voltage of 9 volts, and erase gate EG is applied with a voltage of 0 volt, so that electrons tunnel from the floating gate FG into the substrate, on which memory cell 100 is formed. As a result, floating gate FG will have positive charges (holes). In an erase operation, program gate PG and erase gate EG are both applied with voltages of 9 volts, and hence a high voltage is coupled to floating gate FG. Since floating gate FG has positive charges, the voltage of the floating gate FG is further increased. With source line SL applied with 0V, electrons are injected into floating gate FG through capacitor 104.
Memory cell 100 may be formed simultaneously with the formation of logic circuits. As a result, the non-volatile memory cell 100 suffers from drawbacks. With the increasing down-scaling of integrated circuits, the thicknesses of gate dielectrics in logic circuits are increasingly reduced. Since the non-volatile memory cell 100 needs to be formed simultaneously with logic circuits, the thickness of non-volatile memory cell 100 has to be the same as the thicknesses of logic circuits, which will also be reduced. The reduced thickness of the gate dielectric under the floating gate FG, however, may result in increased leakage current. The data retention ability of non-volatile memory cell 100 is thus degraded accordingly.
FIG. 2 illustrates test results of sample memory cells having the structure shown in FIG. 1, wherein cumulative percentages are illustrated as the function of bit line currents measured from the sample memory cells. The sample memory cells are baked at 250° C. to accelerate the leakage. Measurement results 120 were obtained before the baking, measurement results 122 were obtained after 24 hours of baking, while measurement results 124 were obtained after 72 hours of baking. It was found that before the baking process, none of the sample memory cells failed. However, as the baking proceeded, increasingly more samples failed. After 72 hours of baking, the failure rate reached about 0.1%. The test results revealed the leakage that will occur if the memory cells are stored for a long time. Therefore, non-volatile memory cells having improved reliability are needed.